In this lab, you are expected to address the problem given below, in which you will need to design, implement, and then simulate a digital logic circuit using the Intel® Quartus® Prime FPGA Design Software and produce a detailed report for your submission. attached is project description.pdf
what is needed is as below:
complete logic circuit analysis and design for this decoder as described above, including the truth table, Boolean expressions, and simplification of the Boolean expressions using K-maps.
- Implement the decoder logic circuit using Intel® Quartus® Prime FPGA Design Software as Block Diagram/Schematic file as well as Verilog HDL code.
- Verify your circuit implementation by performing adequate testing.
a. You need to create a waveform file showing the output of all the possible input combinations for your design files (Block Diagram/Schematic file and Verilog HDL code). One waveform is required for each design file.